The invention relates to the field of synchronizing asynchronous data, and in particular to synchronizing read data from an asynchronous peripheral to a bus clock.
Flip-flops are often used as storage elements in digital logic systems. Flip-flops sample their inputs on the rising or falling edge of the clock and continue to hold the sampled input as their output until the next clock edge. Because of the use of flip-flops in digital logic systems, metastability is an important design consideration that almost all designers of digital logic systems must contend with. When a flip-flop goes into a metastable state, its output is unknown and may be between a logic HIGH and a logic LOW, or may be oscillating. If the output does not resolve to a stable value before the next clock edge the metastable condition may be passed to other logic devices connected to the output of the flip-flop. Further, even if the output resolves to a stable value before the next clock edge, the value may be incorrect, causing invalid data to be passed to other logic devices connected to the output of the flip-flop. Metastability arises when a flip-flop input changes during the setup and/or hold time of a flip-flop.
In most digital logic systems, the inputs to the flip-flops do not change during the setup and hold times because the systems are designed as totally synchronous systems, which meet or exceed their components' specifications. In a totally synchronous design, the inputs to the flip-flops have a fixed relationship to the clock, i.e., they are synchronized to the clock. There are some systems, however, in which a totally synchronous design using a single master clock is not possible, or where certain advantages are gained from using an asynchronous design. In these systems, there is a need to interconnect subsystems that have no defined relationship between their clocks, i.e. different clock domains. This often results in a need to provide data from one of the clock domains as an asynchronous input to a flip-flop in the other clock domain. For these systems to function properly, there is a need to synchronize the incoming asynchronous input to the clock domain of the flip-flop. While described in relation to flip-flops, the metastable condition and its associated difficulties also applies to other types of storage elements in a digital logic system, such as latches or combinations of latches.
Such synchronization is often needed for transferring data from asynchronous peripherals to a bus master in a computer system. FIG. 1 illustrates a block diagram of a computer system having an asynchronous peripheral 106. Most modem bus systems provide some type of bus interface logic 100, which controls the transfer of data between a peripheral 106 and a bus master 104 using bus 102. Bus interface logic 100 operates in one clock domain, which may be synchronized to the clock domain of bus master 104. Peripheral 106, however, operates in its own clock domain, which is different from the clock domain of bus interface logic 100. Typically, the frequency of the clock domain of peripheral 106 is slower than the clock domain of bus interface logic 100. When data is being read from asynchronous peripheral 106, it places the data on bus 102. The data on the bus is then sampled using flip-flops set up as a register in either bus interface logic 102 or bus master 104.
Without synchronization of the read data to the bus clock, an asynchronous peripheral may place the data on the bus during the set-up and/or hold times of the flip-flops used by bus interface logic 100, causing one or more of them to go into a metastable state. Therefore, in most systems, peripheral 106 synchronizes the placement of data on bus 102 to the clock domain of bus interface logic 100 using synchronization logic 108 on peripheral 106. Peripheral 106 receives the bus clock and synchronization logic 108 synchronizes the placement of the read data on bus 102 with the bus clock.
FIG. 2 illustrates typical logic on peripheral 106 for outputting read data to bus 102, including synchronization logic 108. For a peripheral to synchronize the data to the bus clock and provide a stable value on the bus, synchronization logic 108 generally requires a read buffer 202 that isolates the internal data change/update inside the peripheral from the read data driven onto the bus. An update_enable signal is asserted to read data that is to be placed on the bus into an internal register 206. Generally, the update_enable signal is long enough to be synchronized to bus clock. However, some applications may use a short update_enable signal with logic that extends the update_enable signal for proper synchronization to the bus clock. Logic 204 then synchronizes the update_enable signal with the bus clock so that the data is transferred to read buffer 202 and, consequently, placed upon the bus in a manner synchronized to the bus clock.
Synchronization performed on each peripheral, however, is disadvantageous because synchronization logic is needed on each peripheral. Further, when synchronization is performed by each peripheral, synchronization is decentralized and not necessarily performed the same way for each peripheral. It would therefore be advantageous to be able to provide stable, valid data from an asynchronous peripheral to a bus master without requiring each peripheral to synchronize its output to the bus clock. More generically, it would be advantageous to provide centralized synchronization for the transportation of data between devices in different clock domains.